1. Field of the Invention
The present invention relates to electronic circuits for generating signals at a desired frequency, and more particularly, to a frequency synthesizer in which the output frequency is adjusted based on comparison of the pulse width of an output signal to a reference signal, and which is capable of generating fractions and multiples of the reference frequency with a fast settling time.
2. Description of the Related Art
A frequency synthesizer is an electronics system or circuit that is used in communication and signal processing systems to generate a range of frequencies from a single stable frequency oscillator. A common approach to realize the frequency synthesizer is based on the Phase Locked Loop (PLL). The PLL is a feedback system which compares the frequencies of its input and output signals; the first component of the PLL system is the frequency or phase detector which carries out the frequency comparison. It is generally understood that error signals, which represents the difference between the input signals, is averaged using a low pass filter (LP) to generate a control signal. The resultant signal is coupled to a VCO to adjust its output frequency. The feedback process is continued to force the error signal to diminish. A frequency divider is inserted in the feedback loop to allow the output frequency to be a multiple of the reference frequency.
One of the desired criteria in the frequency synthesizer system is the fast settling time, which measures the ability of the communication system to perform channels scanning within the allowed acquisition period. Knowing that the loop bandwidth of the frequency synthesizer is inversely related to the settling time, it is therefore recommended to design the system to have a wide loop bandwidth. On the other hand, to minimize spurious emissions generated at the output of the phase detector, it is recommended to select the loop bandwidth to be a tenth of the reference frequency signals Fref. Another disadvantage of the limited loop bandwidth is that it results in high close-in phase noise at the output.
Due to its role in the frequency selection of a frequency synthesizer, a frequency divider has received major attention from researchers in the field. Main types of frequency divider include integer frequency divider and fractional frequency divider.
In the former case, the input frequency and output frequency relation is given by Fout=MFref. M has integer values that are used to control the output frequency. In communication systems, M controls transmitting and receiving frequency channels. Therefore, Fref is constrained to be equal to the channel spacing to allow for channel selection through M, which imposes a limitation on the loop bandwidth of the PLL. Thus a long settling time is one of the main drawbacks of the PLL based integer frequency divider.
Although different frequency divider structures can be used to realize the M divider, typically, a Pulse Swallow divider is widely used. By simple analysis, it can be shown that M and Fout are given by:M=PN+S fout=PNfref+Sfref.
In contrast to the integer frequency divider, a fractional frequency divider allows the output frequency to be a fraction of the reference frequency. Hence, the reference frequency Fref, and consequently the loop bandwidth, can be made much greater than the channel spacing. Thus, the frequency synthesizer-based fractional divider does not suffer from the long settling time. The fractional division ratio is obtained by dividing the output signal by an integer number N for certain number of the output pulses P and by N+1 for another number of S pulses. The effective frequency division ratio M can be given by:
  M  =                    NP        +                              (                          N              +              1                        )                    ⁢          S                            P        +        S              .  
A typical frequency synthesizer circuit comprises a fractional frequency divider. However, a frequency synthesizer-based fractional frequency divider suffers from a series effect called fractional spurs, which are generated from dividing the signal frequency by two different values. Fractional spurs modulate the VCO, and hence strong sideband signals are generated around the output frequency.
Thus, a frequency synthesizer solving the aforementioned problems is desired.